1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same, and more particularly relates to a semiconductor device that controls a timing of latching data and an information processing system including the same.
2. Description of Related Art
Semiconductor devices such as a DRAM (Dynamic Random Access Memory) often control timings of latching data by using a strobe signal (see Japanese Patent Application Laid-open Nos. H4-96419 and 2010-045569). To correctly latch data, it is important to match a timing of a strobe signal to a flow of the data with high accuracy. Accuracy in matching the timing has been more severely required as the speed of the DRAM has become higher.
For this purpose, a type of calibration called “training operation” is sometimes performed at startup of a semiconductor device. The training operation is performed in a system including the semiconductor and a controller that controls the semiconductor device. In the training operation, an appropriate timing range in which the semiconductor device can correctly latch data is scanned and specified by the controller while a timing of a strobe signal supplied by the controller is shifted. Therefore, when the training operation ends, the strobe signal supplied from the controller is matched with write data supplied from the controller with high accuracy.
The system needs to periodically perform the training operation even after startup of the semiconductor because the timing between the write data and the strobe signal may be deviated due to temperature change.
Data accesses to a semiconductor device during the training operation are prohibited. Furthermore, the training requires a certain time. Therefore, overhead or a busy period caused by the training operation reduces performance in a system level. Accordingly, the number of times of calibration operation of the system with respect to temperature changes needs to be reduced.